bullet Advances in Microelectronics: Reviews, Vol.1

   (Open Access Book)

        

  Title: Advances in Microelectronics: Reviews, Vol. 1, Book Series

  Editor: Sergey Y. Yurish

  Publisher: International Frequency Sensor Association (IFSA) Publishing

  Formats: paperback (print book) and printable pdf Acrobat (e-book) 534 pages

  Price: 120.00 EUR (shipping cost by a standard mail without a tracking code is included)

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  Pubdate: 21 December 2018

  ISBN: 978-84-697-8633-8

  e-ISBN: 978-84-697-8634-5

 

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 Advances in Microelectronics: Reviews, Vol. 1, Book Series

 


 

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 Book Description

 

 

Every research and development must be started from a state-of-the-art review, and microelectronics is not an exception. The review is one of the most labor- and time-consuming parts of research. It is strongly necessary to take into account and reflect in the review the current stage of development, including existing technologies, CAD tools and devices. Many PhD students and researchers working in the same area are doing the same type of work. A researcher must find appropriate references, to read it and make a critical analysis to determine what was done well before and what was not solved till now, and determine and formulate his future scientific aim and objectives. The professionally made state-of-the art must take into account not only open access books, articles and conference papers available online for free, but also traditional monographs and journal articles, which are available only off-line and in print (paper) format.

After very successful publication of four volumes of our popular ‘Advances in Sensors: Reviews’ Book Series (2012-2016), it was decided to start publication of new Book Series on ‘Advances in Microelectronics: Reviews’ along with the other Book Series with advances and reviews, which are coming soon.

The 1st volume of new Book Series contains 19 chapters written by 72 authors from academia and industry from 16 countries: Canada, China, Egypt, France, Germany, Iran, Italia, Japan, Malaysia, Norway, Poland, Saudi Arabia, Spain, United Arab Emirates, UK, and USA.

This book ensures that our readers will stay at the cutting edge of the field and get the right and effective start point and road map for the further researches and developments. By this way, they will be able to save more time for productive research activity and eliminate routine work.

 

 

Contents:

 

Contents
Contributors
Preface

 

 

1. Efficient Digital Interpolation Filter


1.1. Introduction
1.1.2. Interpolation
1.1.2.1. Interpolation of a Sampled Signal
1.1.2.2. Digital Interpolation by a Factor of L
1.1.3. Digital Filter
1.1.3.1. Methods to Describe Filters
1.1.3.2. Linear Time-Invariant Digital Filter
1.1.3.3. Finite Impulse Response (FIR) Filters
1.1.3.4. Infinite Impulse Response (IIR) Filters
1.1.3.5. Filtering, Convolution and Correlation
1.1.3.6. Other Filter Structures such as Cascade and Parallel Forms
1.2. FIR Filter Using Sharing Multiplication Technique
1.2.1. FIR Filter Using Sharing Multiplication Technique
1.2.2. Precomputer
1.2.2.1. Adders Types
1.2.3. Shift and Add Unit (S&A)
1.2.3.1. Select Unit
1.2.3.2. Final Adder
1.2.4. Circuit Implementation
1.3. Computational Filter
1.3.1. Computational Filter Operation
1.3.2. Circuit to Realize Mmaj and Mmin
1.3.3. Calculate the Order O(i) Block
1.3.4. Step Selection Block
1.3.5. Filter Implementation
1.4. Simulation Results and Comparison
1.4.1. Matlab Comparison
1.4.2. Modelsim Simulation Results
1.4.2.1. CF Output
1.4.2.2. Validation for Functions of CFIR
1.4.3. FPGA Implementation
1.4.4. Performance Analysis
1.5. Conclusions
References

 

 

2. Potential of Low-Voltage and Low-Energy MOS Devices in Coming Sensor Network Era


2.1. Introduction
2.2. Potential of Silicon-on-Insulator Materials
2.3. Potential and Applications of SOI Devices
2.3.1. Fully-depleted SOI Devices
2.3.2. Cross-Current Tetrode SOI Devices
2.3.3. TBJ SOI MOSFET
2.3.4. Tunnel FET
2.5. Conclusion
Acknowledgements
References

 

 

3. Fabrication and Characterization of High Strength Electrodeposited Gold Toward High-Sensitive MEMS Inertial Sensors


3.1. Introduction
3.2. Constant Current Electrodeposition
3.3. Electrodeposition with Supercritical CO2
3.4. Pulse Current Electrodeposition
3.5. Conclusions
Acknowledgements
References

 

 

4. On the Transimpedance Amplifiers in the Low Frequency Noise Characterization


4.1. Introduction
4.2. Characterizing a Noisy Two-terminal Device
4.3. Measuring the Correlation in Noisy Two-port Networks
4.4. Miniaturizing the TIA
4.5. Conclusions
Acknowledgements
References

 

 

5. Integrated Low-Power Gating Scan Cell for Test Power Minimization


5.1. Introduction
5.2. Literature Review
5.3. Motivation
5.4. Integrated Low Power Gating (ILPG) Scan Cell
5.5. Critical Path Integrated Low Power Gating (CPILPG) Scan Cell
5.6. Partial Gating Application
5.7. Post-Layout Simulation Results and Analysis
5.7.1. Test Average Power Consumption
5.7.2. Shift Power Consumption
5.7.3. Capture Power Consumption
5.7.4. Propagation Delay and Power-Delay-Product (PDP)
5.7.5. Comparative Case Analysis
5.7.6. Area Overhead
5.7.7. Test Quality
5.7.8. Technology Adaptability
5.8. Summary and Conclusion
Acknowledgements
References

 

 

6. Digital Predistortion for Linearization of Wireless Transmitters


6.1. Introduction
6.2. Conventional Linearization Methods of Power Amplifiers
6.2.1. Feedforward
6.2.2. Feedback
6.2.3. Predistortion
6.2.4. Envelope Elimination and Restoration (EER)
6.2.5. Linear Amplification using Nonlinear Components (LINC)
6.3. Behavioral Modeling of Digital Predistortion and Power Amplifiers
6.3.1. Memoryless Model
6.3.1.1. Saleh Model
6.3.1.2. Taylor Series Model
6.3.2. Models with Memory
6.3.2.1. Volterra Series
6.3.2.2. Wiener Model
6.3.2.3. Hammerstein Model
6.3.2.4. Wiener- Hammerstein Model
6.4. Memory Polynomial Model and Model Identification Procedure
6.5. Digital Predistortion
6.6. Performance Assessment of the Digital Predistortion
6.6.1. Providing Power Amplifier Data Set
6.6.2. Identifying Coefficients of the Power Amplifier Model Using the Least Square Algorithm
6.6.3. Identifying Coefficients of the Digital Predistortion Model
6.6.4. Simulation of the Transmitter (PA+DPD)
6.7. Conclusions
References

 

 

7. An Overview of Diffusion Barriers in Cu Interconnection


7.1. Introduction
7.1.1. Cu Metallization
7.1.2. Requirements for Diffusion Barriers
7.2. Preparation and Characterization for Diffusion Barrier
7.2.1. Preparation Methods
7.2.1.1. Physical Vapor Deposition
7.2.1.2. Chemical Vapor Deposition
7.2.1.3. Electrochemical Deposition
7.2.1.4. Atomic Layer Deposition
7.2.1.5. Self-Forming Approach
7.2.2. Characterization Methods
7.2.2.1. Chemical Properties
7.2.2.2. Phase Structure
7.2.2.3. Microtopography
7.2.2.4. Electrical Properties
7.3. Cu Alloy Diffusion Barriers
7.3.1. Microstructure and Properties of Cu Alloy Thin Films
7.3.2. Thermal Stability of Cu Alloy/Si Systems
7.3.3. Self-Forming Diffusion Barriers
7.4. Metal Nitride Diffusion Barrier
7.4.1. Effect of Process Parameter on Zr-Si-N Diffusion Barrier
7.4.2. Thermal Stability of Cu/Zr-Si-N/Si Systems
7.5. Ru-Based Diffusion Barriers
7.5.1. Element Doping in Ru-Based Films
7.5.2. Thermal Stability of Ru-Based Diffusion Barriers
7.6. ZrB2-Based Diffusion Barriers
7.6.1. Nano-Grained ZrB2 Diffusion Barrier
7.6.3. Amorphous ZrBxOy Diffusion Barrier
7.7. Conclusion
Acknowledgements
References

 

 

8. Metrology and Inspection Solutions for Fan-Out Wafer Level Packaging


8.1. Introduction
8.2. Fan-out Wafer Level Packaging
8.3. Metrology and Inspection in the FOWLP
8.3.1. Singulation: Kerf Metrology
8.3.2. Re-Constitution: Die Placement Accuracy
8.3.3. Redistribution Layer
8.3.4. Characterization of Under Bump Metallization
8.3.5. Characterization of Photoresists and Polymeric Materials
8.3.6. Thickness and Uniformity Characterization
8.3.7. Detection of Residue and Non-Visual Killer Defects
8.3.8. Characterization of RDL
8.3.9. CD Overlay Metrology
8.3.10. Characterization of Wafer Bow
8.4. Bump Metrology
8.5. Data Analytics
8.6. Conclusions
Acknowledgments
References

 

 

9. Electrothermal Modeling of GaN HEMTs


9.1. Introduction
9.2. Thermal and Trapping Induced Kink Effect
9.3. Table-Based DC IV Model
9.4. Analytical DC IV Model
9.4.1. Model Parameters Optimization Using Genetic-Algorithm
9.5. Inverse Class-F Power Amplifier
9.6. Conclusion
Acknowledgements
References

 

 

10. Hot Carrier Injection (HCI) of High-k/Metal Gate MOSFET with Gate-Last Process


10.1. Reliability of HKMG MOSFET with Gate-Last Process
10.2. Hot Carrier Injection Characteristics of HKMG MOSFET
10.2.1. Peak-Isub Stress
10.2.2. Vg=Vd Stress
10.3. Coupling between HCI and BTI
10.3.1. A Method to Separate “Hot” Carrier and “Cold” Carrier Using DIBL
10.3.2. Separation of “Hot Carrier” and “Cold Carrier”
10.4. Physical Mechanisms of HCI
10.5. HCI Lifetime Extrapolation
10.5.1. Power-law of TTF and Isub
10.5.2. Two-Step in Curve of TTF and Isub
10.6. Conclusions
References

 

 

11. Sol-Gel Oxides Spin-Coating and Dye-Sensitized Solar Cell Performance


11.1. Introduction
11.2. Experimental Methods
11.3. Results and Discussions
11.3.1. ZnO Results
11.3.2. MgO Results
11.4. Conclusion
Acknowledgements
References

 

 

12. Review of the Reliability of Flexible Packaging of Thin and Ultra-Thin ICs


12.1. Introduction and Background
12.2. Measurement of Fracture Strength of Thin and Ultra-Thin ICs
12.3. Mechanical Stress Analysis of Thin and Ultra-Thin Silicon Dies in Flex Packaging
12.4. Recurrent Bending Tests of the Flexible Packages
12.4.1. Fixed-Radius Bending Test
12.4.2. Free-Form Bending Test
12.5. Embedded IC – Chip-in-Foil Approach
12.6. Conclusions
Acknowledgements
References

 

 

13. Thermal Contact Resistance within Press Pack IGBTs


13.1. Background and Challenges
13.1.1. Opportunities for Press Pack IGBTs
13.1.2. Challenges for Press Pack IGBTs
13.1.3. Thermal Contact Resistance within Press Pack IGBTs
13.2. Finite Element Simulation
13.2.1. Theoretical Model
13.2.1.1. Micro-Contact Conductance hs
13.2.1.2. Micro-Gap Conductance hg
13.2.2. Finite Element Model
13.2.3. Simulation Results and Analysis
13.2.3.1. Influence of the Temperature
13.2.3.2. Influence of the Clamping Force
13.3. Experimental Measurement
13.3.1. Combination Method
13.3.2. Indirect Experiment Method
13.3.2.1. Influence of the Temperature
13.3.2.2. Influence of the Clamping Force
13.4. Optimization
13.4.1. The Demand for Optimization
13.4.2. Nanosilver Sintering Technology
13.4.3. Experimental Results
13.5. Conclusion and Outlook
References

 

 

14. Reliability Study on Nanoscale CMOS Devices


14.1. Introduction
14.2. Reliability Study on Nanoscale Traditional CMOS Devices
14.2.1. Extraction of Interface Traps
14.2.1.1. Extraction of the Average Density of Interface Traps
14.2.1.2. Front and Back Gate Interface and Oxide Traps in SOI MOSFETs
14.2.1.3. Extraction of the Lateral Spatial Distribution of Interface Traps
14.2.2. Negative Bias Temperature Instability Effect
14.3. Reliability Study on Nanoscale Non-Traditional CMOS Devices
14.3.1. Reliability of FinFETs
14.3.1.1. Generation of Interface State Traps in FinFETs
14.3.1.2. Temperature Dependence of Interface States in FinFETs
14.3.1.3. Asymmetric Issues of FinFETs
14.3.2. Reliability of Nanowire MOSFETs
14.3.2.1. NBTI Model for Nanowire MOSFETs
14.3.2.2. Suppression of Tunneling Leakage Current in Nanowire MOSFETs
14.4. Variation Study on Nanoscale Novel MOSFET Devices
14.4.1. Random Dopant Fluctuation Effect
14.4.2. Fin-Width Line Edge Roughness Effect
14.4.3. Fin Sidewall Angle Fluctuation Effect
14.5. Conclusions
Acknowledgements
References

 

 

15. Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip


15.1. Introduction
15.2. Related Work
15.3. Fault Tolerant Routing with CAFTA
15.3.1. Router Architecture
15.3.2. Fault Model and Assumptions
15.3.3. Routing Algorithm
15.3.4. Network Traffic Regulation with the FR Metric
15.3.5. Message Recovery
15.3.6. Extension of CAFTA for Torus Topology
15.3.6.1. Routing and Deadlocks in 2D torus NoC
15.3.6.2. Vertical Wrapping Links
15.3.6.3. Horizontal Wrapping Links
15.3.6.4. Vertical and Horizontal Wrapping Links
15.4. Experimental Setup and Results
15.4.1. Experimental Setup
15.4.2. Performance of FR Metric Under Synthetic Traffic
15.4.3. Variation of Average Latency Due to the Presence of Faults Under Synthetic Traffic
15.4.4. Reliability Estimation
15.4.5. CAFTA for Torus NOC Topology
15.5. Conclusions
References

 

 

16. Wearable Data Collecting and Processing Hub for Personal Vital Signs Measurement


16.1. Introduction
16.2. Related Work
16.2.1. Intelligent Sensors for Physiological Signals
16.2.2. Computer Systems for Biosignals Measurements
16.2.3. Dedicated Portable Systems for Biosignal Measurements
16.3. Central Hub Hardware and Management Rules
16.3.1. Biosignal Interface
16.3.2. Sensor Network Management Module
16.3.3. Device Management Kernel
16.3.4. Storage and Communication Module
16.4. Building a Network of Cooperating Sensors
16.5. Sensor Management Protocols
16.6. Data Processing Platforms
16.6.1. Wearable Data Processing Platform
16.6.2. Central Data Processing Platform
16.7. Discussion
Acknowledgment
References

 

 

17. Challenges and Approaches for Assurance of Safety-Critical Programmable Hardware


17.1. Introduction
17.2. Challenges in Assurance
17.3. Assurance Standards
17.4. Assurance of Developer’s Hardware Development
17.5. Assurance of Hardware COTS and IP Items
17.6. Formal Approaches to Hardware Assurance
17.6.1. Case Study
17.6.1.1. Plant
17.6.1.2. Controller
17.6.1.3. Analysis of the Controller Petri Net Model
17.6.1.4. CSS Analysis for the Pump Control System
17.7. Conclusion
References

 

 

18. Reliability-Aware Energy Management for Weakly Hard Real-Time Systems


18.1. Introduction
18.2. Preliminary
18.2.1. System Model
18.2.2. Fault and Recovery Models
18.2.3. Power Model
18.2.4. Practical Critical Speed
18.2.5. Tradeoff between the Practical Critical Speed and Pure DVS Speed
18.2.6. Computing the Overall Energy-Efficient Speed
18.2.7. Meeting the (m, k)-constraint
18.3. The General Algorithm
18.3.1. Computing the LST for the Upcoming Mandatory/Recovery Jobs
18.3.1.1. Computing LST with Exact Timing Analysis
18.3.1.2. More Efficient Conditions in Computing LST
18.4. Online Slack Reclaiming
18.5. Experimental Results
18.5.1. Experimental Results from Synthesized Task Sets
18.5.2. Experimental Results from Practical Applications
18.6. Related Work
18.7. Conclusions
References
Appendix A. Proof for Theorem 5
Appendix B. Proof for Theorem 2

 

 

19. Faking Countermeasure against Side-Channel Attacks


19.1. Introduction
19.2. Fundamentals
19.2.1. AES Algorithm
19.2.2. AES Vulnerabilities
19.3. The FAKING Countermeasure
19.3.1. Added Vulnerabilities
19.3.1.1. Second Order Attack
19.3.1.2. Attack on the Output of SboxTrans
19.3.2. Protecting the StM TRANS Array
19.3.3. Computational Cost
19.4. Experimental Results
19.5. Conclusions
Acknowledgements
References

 

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