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Vol. 193, Issue 10, October 2015, pp. 41-49




Sub-nanosecond Gating of Large CMOS Imagers

Octavian Maciu, Wilfried Uhring, Jean-Pierre Le Normand, Jean-Baptiste Kammerer, Foudil Dadouche, Norbert Dumas

ICube, UMR 7357, University of Strasbourg and CNRS 23, rue du Loess BP 20, F-67037 Strasbourg Cedex 2, France
Tel.: +33 (0)3 88 10 68 27, fax: +33 (0) 3 88 10 65 48

E-mail: wilfried.uhring@unistra.fr


Received: 31 August 2015 /Accepted: 5 October 2015 /Published: 30 October 2015

Digital Sensors and Sensor Sysstems


Abstract: Ultra-fast gating of large array imagers can be quite challenging to implement due to the distributed RC (Resistance Capacitance) nature of the metal wires used in all ICs (Integrated Circuits) for electrical connections. For the transmission of a signal across a long path, the metal line reduces the electrical bandwidth and adds a delay. The behavior of these lines has been modeled and a new solution is presented to circumvent these limitations. In this paper, we present an edge-based approach to the gating circuitry that allows sub nanosecond gating with a very low skew across the whole imager. Simulation data shows that our solution is an efficient way of reducing the effect of the distributed RC line delay with a small penalty on surface area and consumption.


Keywords: SPAD, Ultra-fast gating, Edge-triggered, Fast pulse, Skewless.


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