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Vol. 193, Issue 10, October 2015, pp. 123-134




New Design-methodology of High-performance TDC on a Low Cost FPGA Targets

Foudil Dadouche, Timothé Turko, Wilfried Uhring, Imane Malass, Norbert Dumas, Jean-Pierre Le Normand

ICube, UMR 7357, University of Strasbourg and CNRS 23, rue du Loess BP 20, F-67037 Strasbourg Cedex 2, France
Tel.: +33 (0)3 88 10 68 27, fax: +33 (0)3 88 10 65 48

E-mail: wilfried.uhring@unistra.fr


Received: 31 August 2015 /Accepted: 5 October 2015 /Published: 30 October 2015

Digital Sensors and Sensor Sysstems


Abstract: This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the system in user specified physical regions. This allows the placement of TDC partitions so that the routing paths are constrained. As a result, the user controls the propagation delay effectively through the connection network. The paper ends by applying the presented methodology to a case study showing the design and implementation of high resolution TDC dedicated to time correlated single photon counting system. The resolution of 42 ps as well as the INL, DNL and mean Jitter values (22 ps rms, 13 ps rms and 26 ps rms, respectively) obtained using a low cost FPGA target Cyclone family are very promising and suitable for a large amount of fast applications.


Keywords: Time-to-digital converter, FPGA, Chip planner, Carry chain logic, Time correlated single photon counting.


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