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Vol. 22, Special Issue, June 2013, pp. 29-35




A High Precision and Low Power Digital Synchronous Clock for Sensor Network
1 Jie Wu, 1 Liefeng Liu, 1 Jie Zhang, 1 Zhao Han, 1 Kaiyun Tian, 1 Juan Dong, 2 Yichao Ma

1 Department of Modern Physics, University of Science and Technology of China, Hefei, Anhui, 230026, China

2 College of Electrical and Information Engineering, Shaanxi University of Science and Technology, Xi'an, Shaanxi, 710021, China

Tel.: +86 (551) 63606496, fax: +86 (551) 63603432

E-mail: wujie@ustc.edu.cn


Received: 15 April 2013   /Accepted: 20 June 2013   /Published: 28 June 2013

Digital Sensors and Sensor Sysstems


Abstract: The applications envisioned for sensor networks require collaborative execution of a distributed task amongst a large set of sensor nodes. This is realized by exchanging messages that are time-stamped using the local clocks on the nodes. Therefore, time synchronization becomes an indispensable piece of infrastructure in such systems. We propose a design of synchronous clock using digital tune method. It combines the factor of traditional way of network time protocol (NTP) and clock data recovery (CDR) to generate a low power and high precision synchronous clock between nodes. It uses DAC and voltage-controlled oscillator (VCXO) to act as local variable clock source, and by exchanging sync frames it measures the transfer propagation and time offset of two nodes. With this information, a fast convergence algorithm like successive approximation makes the clocks match well fast. A digital synchronous clock (DSC) eliminates the need of continually communication between two devices, which is used in CDR, and shows much more accuracy synchronization than NTP. When the DSC is in fine tune state, only low overhead communications are needed to maintain the synchronization of the clocks. The results shows that DSC can make the frequency difference of two clocks reduce to as low as 0.1 ppm. Compare to the accuracy of normal crystal (50 ppm), it is 5102 better. While it is used to generate a synchronous pulse, the synchronization error of the pulse is better than 180 ns (3s, the alarm time is about one second).


Keywords: Digital clock, Distributed clock, Low power, Sensor network, Synchronization.


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