Vol. 145, No. 10, September 2012, pp. 183-190

Abstract: In this paper, an efficient design scheme for implementation of the Proportional-Integral-Derivative (PID) controller using Field Programmable Gate Array (FPGA) technology is presented. The algorithm is implemented using a scheme where a Look-Up-Table (LUT) mechanism inside the FPGA is utilized. A design which is efficient in terms of power consumption and chip area while having adequate speed means that the FPGA chip can be used to accommodate more controllers with low power consumption, resulting in a cost reduction of the controller hardware.

Keywords: FPGA design, Dynamic system, PmodAD1, PID controller, VHDL, Chip scope analyzer

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