Vol. 235, Issue 7, July 2019, pp. 15-22

Abstract: This paper describes a methodology to combine the most scalable FinFET structure and CMOS integration processing to form stacked FinFET-CMOS technology used in 3-D integration circuits. The scalability of the proposed 3-D technology in the nanocale dimension is achieved through the promise of the double- gate structure offered by the FinFETs. The stack FinFET-CMOS process is realized in FEOL processing and can achieve extremely high packing density, which results in the 40 to 60 % reduction of capacitive loading. Various standard cells have been re- designed by the FinFET-CMOS technology resulting in significant reduction in cell size. The advantages in conventional circuit performance with the new 3-D standard cell library have also been demonstrated.

Keywords: FinFET, 3-D integration circuits, Processing technology, Performance enhancement, Capacitive load.

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